The present invention relates generally to integrated circuit devices and, more particularly, to coupling piezoelectric material generated stresses to devices formed in integrated circuits.
Complementary Field Effect Transistors (FETs) support the standard computer architecture (CMOS) currently used in logic and memory. FETs exploit high channel mobility to control few-carrier currents electrostatically. However, limitations in this highly successful technology are appearing at current and future device scales.
More specifically, difficulties in scalability arise from short channel effects and from few-dopant fluctuation effects. The HfO2 gate oxide short channel solution brings about mobility limitations which are slowing clock speeds (Moore's Law scaling becomes negative). The unfavorable FET geometry wherein the gate capacitance corresponds to gate area, but wherein current corresponds to channel width/channel length (resulting in a speed ˜1/L2), means that the FET is a relatively high impedance device. Hence undesirably large-area FETs are required in “power hungry” applications, such as programming a PCM memory, driving long wires, or shutting down power to inactive circuit blocks.
It is desirable but very complex to build multi-layer structures in CMOS, due to the need for all FETs to be formed in single crystal silicon. A new technology in which straightforward lithographic processes can build multilayer structures could open up significant new applications such as high capacity multilayer memories and combinations of logic and memory at different levels optimized to reduce wiring length.